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document no. e1242e20 (ver. 2.0) date published february 2008 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2007-2008 preliminary data sheet 8gb fully buffered dimm ebe82ff4a1rq specifications ? density: 8gb ? organization ? 1024m words 72 bits, 4 ranks ? mounting 36 pieces of 2g bits ddr2 sdram with ddp (fbga) ? ddp: 2 pieces of 1gb chips sealed in one package ? package ? 240-pin fully buffered, socket type dual in line memory module (fb-dimm) pcb height: 30.35mm lead pitch: 1.00mm ? advanced memory buffer (amb): 655-ball fcbga ? lead-free (rohs compliant) ? power supply ? ddr2 sdram: vdd = 1.8v 0.1v ? amb: vcc = 1.5v + 0.075v/ ? 0.045v ? data rate: 667mbps (max.) ? eight internal banks for concurrent operation (components) ? interface: sstl_18 ? burst lengths (bl): 4, 8 ? /cas latency (cl): 3, 4, 5 ? precharge: auto precharge option for each burst access ? refresh: auto-refresh, self-refresh ? refresh cycles: 8192 cycles/64ms ? average refresh period 7.8 s at 0 c tc + 85 c 3.9 s at + 85 c < tc + 95 c ? operating case temperature range ? tc = 0 c to +95 c features ? jedec standard raw card aa design ? industry standard advanced memory buffer (amb) ? high-speed differential point-to-point link interface at 1.5v (jedec spec) ? 14 north-bound (nb) high speed serial lanes ? 10 south-bound (sb) high speed serial lanes ? various features/modes: ? membist and ibist test functions ? transparent mode and direct access mode for dram testing ? interface for a thermal sensor and status indicator ? channel error detection and reporting ? automatic ddr2 sdram bus and channel calibration ? spd (serial presence detect) with 1piece of 256 byte serial eeprom note: warranty void if removed dimm heat spreader. performance fb-dimm ddr2 sdram system clock frequency speed grade peak channel throughput fb-dimm link data rate speed grade ddr data rate 167mhz pc2-5300f 8.0gbyte/s 4.0gbps ddr2-667 (5-5-5) 667mbps
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 2 ordering information part number dimm speed grade component jedec speed bin (cl-trcd-trp) mounted devices* 1 mounted amb* 2 EBE82FF4A1RQ-6E-E pc2-5300f ddr2-667 (5-5-5) 2g bits ddr2 sdram idt rev. d0 notes: 1. please refer to 1gb ddr2 datasheet (e0975e) for electrical characteristics. 2. please refer to the following documents for detailed operation part and timing waveforms. advanced memory buffer (amb) specification fb-dimm architecture and protocol specification part number elpida memory density / rank 82: 8gb/4-rank module type f: fully buffered mono density f: 2gbit die rev. (mono) dram speed grade 6e: ddr2-667 (5-5-5) product family e: ddr2 type b: module power supply, interface a: 1.8v, sstl_1.8 module outline r: 240-pin dimm (ddp) amb device information q: idt, rev.d0 mono organization 4: x4 e b e 82 f f 4 a 1 r q - 6e - e environment code e: lead free (rohs compliant)
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 3 advanced memory buffer overview the advanced memory buffer (amb) reference design comp lies with the fb-dimm architecture and protocol specification. it supports ddr2 sdram main memory. t he amb allows buffering of memo ry traffic to support large memory capacities. all memory contro l for the dram resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configur ation access, and power management. the amb interface is responsible for handling fb-dimm channel and memory requests to and from the local dimm and for forwarding requests to other dimms on the fb-dimm channel. the fb-dimm provides a high memory bandwidth, large capac ity channel solution that has a narrow host interface. fb-dimms use commodity drams isolated from the channel behind a buffer on the dimm. the memory capacity is 288 devices per channel and total memory capacity scales with dram bit density. the amb is the buffer that isolat es the drams from the channel. advanced memory buffer functionality the amb will perform the following fb-dimm channel functions. ? supports channel initialization procedur es as defined in the initialization ch apter of the fb-dimm architecture and protocol specification to al ign the clocks and the frame boundaries, verify channel connectivity, and identify amb dimm position. ? supports the forwarding of southbound and northbound fram es, servicing requests directed to a specific amb or dimm, as defined in the protocol chapter, and me rging the return data into the northbound frames. ? if the amb resides on the last dimm in the ch annel, the amb initializes northbound frames. ? detects errors on the channel and reports them to the host memory controller. ? support the fb-dimm configurat ion register set as defined in the register chapters. ? acts as dram memory buffer for all read, write, and configuration accesse s addressed to the dimm. ? provides a read buffer fifo and a write buffer fifo. ? supports an smbus protocol interface for ac cess to the amb configuration registers. ? provides logic to support membist and ibist design for test functions. ? provides a register interface for the thermal sensor and status indicator. ? functions as a repeater to extend t he maximum length of fb-dimm links.
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 4 advanced memory buffer block diagram demux piso mux mux mux mux link init sm and control and csrs link init sm and control and csrs sync & idle pattern generator ibist-tx failover failover dram command command out dram clock 4 dram data and strobes dram address and command copy1 data in data out pll reset control thermal sensor dram interface core controller and csrs lai controller smbus controller command decoder & crc check data crc generator and read fifo reference clock /reset smbus write data fifo lai logic nb lai buffer init patterns ddr state controller and csrs external membist ddr calibration re-synch 10 2 1 2 re-time southbound data in 10 2 10 12 10 12 southbound data out data merge piso re-synch 14 6 2 re-time northbound data out northbound data in 14 214 2 14 12 demux dram clock 4 24 dram address and command copy2 24 72+18 2 data merge ibist-rx ibist-rx ibist-tx dram chip select 4 a2 for the ecc drams a6 for the ecc drams note: this figure is a conceptual block diagram of the amb?s data flow and clock domains.
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 5 interfaces figure block diagram amb interfaces shows the amb and all of its interfaces. they consist of two fb-dimm links, one ddr2 channel and an smbus interface. each fb-dimm link connects the amb to a host memory controller or an adjacent fb-dimm. the ddr2 channel supports di rect connection to the ddr2 sdrams on an fb-dimm. memory interface secondary or to optional next fbd primary or host direction nb fbd in link sb fbd out link sb fbd in link nb fbd out link smb amb block diagram amb interfaces interface topology the fb-dimm channel uses a daisy-chain topology to provide expansion from a single dimm per channel to up to 8 dimms per channel. the host sends da ta on the southbound link to the first dimm where it is received and redriven to the second dimm. on the southbou nd data path each dimm receives the data and again re-drives the data to the next dimm until the last dimm receives the data. the last dimm in the chain initiates the transmission of data in the direction on the host (a.k.a. northbound). on the north bound data path each dimm receives the data and re-drives the data to the next dimm until the host is reached. amb host southbound n/c n/c nourthbound amb amb amb block diagram fb-dimm channel southbound and northbound paths
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 6 high-speed differential point-to-poi nt link (at 1.5 v) interfaces the amb supports one fb-dimm channel consisting of two bidi rectional link interfaces using high-speed differential point-to-point electrical signaling. the southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent dimm in the host direction. the so uthbound output link forwards this same data to the next fb-dimm. the northbound input link is 14 lanes wide and carries read return data or status information from the next fb-di mm in the chain back towards the host. the northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally. data and commands sent to the drams travel southbound on 10 primary differential signal line pairs. data received from the drams and status information travel northbound on 14 primary differential pairs. data and commands sent to the adjacent dimm upstream are re peated and travel further southbound on 10 secondary differential pairs. data and status information received from the adjacent dimm upstream travel further northbound on 14 secondary differential pairs. ddr2 channel the ddr2 channel on the amb supports direct connection to ddr2 sdrams. the ddr2 channel supports four ranks of eight banks with 15 row/column request, 64 data, and eight check-bit signals. there are two copies of address and command signals excluding chip select, to supp ort dimm routing and electrical requirements. four transfer bursts are driven on the data and check-bit li nes at 667mhz. propagation de lays between read data/check- bit strobe lanes on a given channel can differ. each st robe can be calibrated by hardw are state machines using write/read trial and error. hardware aligns the read data and check-bits to a single core clock. the amb provides four copies of the command clock phase references (clk [3:0]) and write data/check-bit strobes (dqss) for each dram nibble. smbus slave interface the amb supports an smbus interface to allow system acce ss to configuration register independent of the fb-dimm link. the amb will never be a master on the smbus, only a slave. serial smbus data transfer is supported at 100khz. smbus access to the amb may be a requirement to boot and to set link strength, frequency and other parameters needed to insure robust configurations. it is also required for diagnostic support when the link is down. the smbus address straps located on the dimm connector are used by the unique id.
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 7 block diagram dm /cs dqs /dqs dq0 to dq3 4 dqs0 d0 /cs0 vss dq4 to dq7 4 dqs9 /dqs0 d1 /dqs9 4 dq8 to dq11 dqs1 d2 /dqs1 dq12 to dq15 dqs10 d3 /dqs10 dq16 to dq19 dqs2 d4 /dqs2 dq20 to dq23 dqs11 d5 /dqs11 dq24 to dq27 dqs3 d6 /dqs3 dq28 to dq31 dqs12 /dqs12 cb0 to cb3 dqs8 dq0 to dq3 d8 /dqs8 d36 d37 d38 d39 d40 d41 d42 d43 d44 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 /cs1 d18 d19 d20 d21 d22 d23 dq0 to dq3 d26 d54 d55 d56 d57 d58 d59 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 4 4 dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs /cs3 /cs2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 d24 d60 dq0 to dq3 dq0 to dq3 dm /cs dqs /dqs dm /cs dqs /dqs d25 d61 dq0 to dq3 dq0 to dq3 dm /cs dqs /dqs dm /cs dqs /dqs d62 dq0 to dq3 dm /cs dqs /dqs d7 dq0 to dq3 dm /cs dqs /dqs block diagram (1)
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 8 dm /cs dqs /dqs dq32 to dq35 4 dqs4 d9 /cs0 vss dq36 to dq39 dqs13 /dqs4 d10 /dqs13 dq40 to dq43 dqs5 d11 /dqs5 dqs14 d12 /dqs14 dq48 to dq51 dqs6 d13 /dqs6 dq52 to dq55 dqs15 d14 /dqs15 dq56 to dq59 dqs7 d15 /dqs7 dq60 to dq63 dqs16 d16 /dqs16 cb4 to cb7 dqs17 dq0 to dq3 d17 /dqs17 d45 d46 d47 d48 d49 d50 d51 d52 d53 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 /cs1 d27 d28 d29 d30 d31 d32 d33 d34 dq0 to dq3 d35 d63 d64 d65 d66 d67 d68 d69 d70 d71 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 dq0 to dq3 4 dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dm /cs dqs /dqs dq44 to dq47 all address/command/control/clock a m b pn0 to pn13 /pn0 to /pn13 ps0 to ps9 /ps0 to /ps9 dq0 to dq63 cb0 to cb7 dqs0 to dqs17 /dqs0 to /dqs17 scl sda sa1 to sa2 sa0 /reset sck/ /sck notes: 1. dq wiring may be changed within a nibble. 2. there are two physical copies of each address/command/control excluding cs. 3. there are four physical copies of each clock. 4. ecca2 and ecca6 does not use(nc). 5. odt pin(d0-d35) is connected to vss. sn0 to sn13 /sn0 to /sn13 ss0 to ss9 /ss0 to /ss9 /cs0 -> /cs (d36 to d53) /cs1 -> /cs (d54 to d71) /cs2 -> /cs (d0 to d17) /cs3 -> /cs (d18 to d35) cke0 -> cke (d0 to d17,d36 to d53) cke1 -> cke (d18 to d35,d54 to d71) odt -> odt (d36 to d71) ba0 to ba2 (all sdrams) a0 to a13 (all sdrams) ecca2,ecca6 -> nc /ras (all sdrams) /cas (all sdrams) /we (all sdrams) ck/ /ck (all sdrams) vtt sda scl serial pd wp a0 a1 a2 sa0 sa1 sa2 u0 vtt vcc vdd vref vss vddspd terminators amb d0 to d71 , amb d0 to d71 d0 to d71 , spd, amb spd, amb * d0 to d71 : 1g bits ddr2 sdram u0 : 256 bytes eeprom /cs3 /cs2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 scl sda block diagram (2)
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 9 pin configurations 1 pin front side back side 68 pin 69 pin 120 pin 121 pin 188 pin 189 pin 240 pin front side back side no. name no. name no. name no. name no. name no. name no. name no. name 1 vdd 36 vss 71 /ps0 106 nc 121 vdd 156 vss 191 /ss0 226 nc 2 vdd 37 pn5 72 vss 107 vss 122 vdd 157 sn5 192 vss 227 vss 3 vdd 38 /pn5 73 ps1 108 vdd 123 vdd 158 /sn5 193 ss1 228 sck 4 vss 39 vss 74 /ps1 109 vdd 124 vss 159 vss 194 /ss1 229 /sck 5 vdd 40 pn13 75 vss 110 vss 125 vdd 160 sn13 195 vss 230 vss 6 vdd 41 /pn13 76 ps2 111 vdd 126 vdd 161 /sn13 196 ss2 231 vdd 7 vdd 42 vss 77 /ps2 112 vdd 127 vdd 162 vss 197 /ss2 232 vdd 8 vss 43 vss 78 vss 113 vdd 128 vss 163 vss 198 vss 233 vdd 9 vcc 44 nc 79 ps3 114 vss 129 vcc 164 nc 199 ss3 234 vss 10 vcc 45 nc 80 /ps3 115 vdd 130 vcc 165 nc 200 /ss3 235 vdd 11 vss 46 vss 81 vss 116 vdd 131 vss 166 vss 201 vss 236 vdd 12 vcc 47 vss 82 ps4 117 vtt 132 vcc 167 vss 202 ss4 237 vtt 13 vcc 48 pn12 83 /ps4 118 sa2 133 vcc 168 sn12 203 /ss4 238 vddspd 14 vss 49 /pn12 84 vss 119 sda 134 vss 169 /sn12 204 vss 239 sa0 15 vtt 50 vss 85 vss 120 scl 135 vtt 170 vss 205 vss 240 sa1 16 vid1 51 pn6 86 nc 136 vid0 171 sn6 206 nc 17 /reset 52 /pn6 87 nc 137 m_test 172 /sn6 207 nc 18 vss 53 vss 88 vss 138 vss 173 vss 208 vss 19 nc 54 pn7 89 vss 139 nc 174 sn7 209 vss 20 nc 55 /pn7 90 ps9 140 nc 175 /sn7 210 ss9 21 vss 56 vss 91 /ps9 141 vss 176 vss 211 /ss9 22 pn0 57 pn8 92 vss 142 sn0 177 sn8 212 vss 23 /pn0 58 /pn8 93 ps5 143 /sn0 178 /sn8 213 ss5 24 vss 59 vss 94 /ps5 144 vss 179 vss 214 /ss5 25 pn1 60 pn9 95 vss 145 sn1 180 sn9 215 vss 26 /pn1 61 /pn9 96 ps6 146 /sn1 181 /sn9 216 ss6 27 vss 62 vss 97 /ps6 147 vss 182 vss 217 /ss6 28 pn2 63 pn10 98 vss 148 sn2 183 sn10 218 vss 29 /pn2 64 /pn10 99 ps7 149 /sn2 184 /sn10 219 ss7 30 vss 65 vss 100 /ps7 150 vss 185 vss 220 /ss7 31 pn3 66 pn11 101 vss 151 sn3 186 sn11 221 vss 32 /pn3 67 /pn11 102 ps8 152 /sn3 187 /sn11 222 ss8 33 vss 68 vss 103 /ps8 153 vss 188 vss 223 /ss8 34 pn4 69 vss 104 vss 154 sn4 189 vss 224 vss 35 /pn4 70 ps0 105 nc 155 /sn4 190 ss0 225 nc
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 10 pin description pin name pin type function sck, /sck input system clock input pn0 to pn13, /pn0 to /pn13 output primary northbound data ps0 to ps9, /ps0 to /ps9 input primary southbound data sn0 to sn13, /sn0 to /sn13 input secondary northbound data ss0 to ss9, /ss0 to /ss9 output secondary southbound data scl input serial presence detect (spd) clock input sda input / output spd data and amb smbus address/data sa0 to sa2* 1 input spd address inputs vid0 to vid1* 2 input voltage id /reset input amb reset signal m_test* 3 input vref margin test input nc ? no connection vcc power supply amb core power and amb channel interface power (1.5v) vdd power supply dram power and amb dram i/o power (1.8v) vtt power supply dram address, command and clock termination voltage (vdd/2) vddspd power supply spd power (3.3v) vss ? ground notes: 1. they are also used to select the dimm number in the amb. 2. these pins must be unconnected. 3. don?t connect in a system.
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 11 electrical specifications ? all voltages are referenced to vss (gnd). absolute maximum ratings parameter symbol value unit note voltage on any pin relative to vss vin/vout ?0.3 to +1.75 v amb core power voltage relative to vss vcc ?0.3 to +1.75 v dram interface power voltage relative to vss vdd ?0.5 to +2.30 v termination voltage relative to vss vtt ?0.5 to +2.30 v storage temperature tstg ?55 to +100 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating temperature conditions parameter symbol value unit note sdram component case temperature tc _ dram 0 to + 95 c 1 amb component case temperature tc _ amb 110 c note: 1. supporting 0c to +85c and being able to extend to +95c with doubling auto-refresh commands in frequency to a 32ms period (trefi = 3.9 s) and higher temperature self-refresh entry via the control of emrs (2) bit a7 is required. dc operating conditions parameter symbol min. typ. max. unit note amb supply voltage vcc 1.455 1.50 1.575 v ddr2 sdram supply voltage vdd 1.7 1.8 1.9 v input termination voltage vtt 0.48 vdd 0.50 vdd 0.52 vdd v eeprom supply voltage vddspd 3.0 3.3 3.6 v spd input high voltage vih (dc) 2.1 ? vddspd v 1 spd input low voltage vil (dc) ? ? 0.8 v 1 reset input high voltage vih (dc) 1.0 ? ? v 2 reset input low voltage vil (dc) ? ? 0.5 v 2 leakage current (reset) il ?90 ? 90 a 2 leakage current (link) il ?5 ? 5 a 3 notes: 1. applies for smb and spd bus signals. 2. applies for amb cmos signal /reset. 3. for all other amb related dc parameters, please refer to the high-speed differential link interface specification.
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 12 amb component timing for purposes of idd testing, the fo llowing parameters are to be utilized. parameter symbol min. typ. max. units note ei assertion pass-thru timing tei propagate ? ? 4 clks ei deassertion pass-thru timing teid ? ? bit lock clks ei assertion duration tei 100 ? ? clks resample pass-thru time ? 1.075 ? ns resynch pass-thru time ? 2.075 ? ns bit lock interval tbitlock ? ? 119 frames frame lock interval tframelock ? ? 154 frames note: 1. the ei stands for electrical idle . power specification parameter and test conditions -6e frequency (mbps) 667 parameter symbol power supply max. unit conditions note @1.5v 2.60 a @1.8v 3.15 a idle current, single or last dimm idd_idle_0 total 9.23 w l0 state, idle (0 bw) primary channel enabled, secondary channel disabled cke high. command and address lines stable. dram clock active. @1.5v 3.40 a @1.8v 3.14 a idle current, first dimm idd_idle_1 total 10.47 w l0 state, idle (0 bw) primary and secondary channels enabled cke high. command and address lines stable. dram clock active. @1.5v 3.90 a @1.8v 5.70 a active power idd_active_1 total 16.12 w l0 state 50% dram bw, 67% read, 33% write. primary and secondary channels enabled. dram clock active, cke high. @1.5v 3.70 a @1.8v 3.13 a active power, data pass through idd_active_2 total 10.92 w l0 state 50% dram bw to downstream dimm, 67% read, 33% write. primary and secondary channels enabled. cke high. command and address lines stable. dram clock active. @1.5v 4.00 a @1.8v 2.95 a training idd_training (for amb spec. not in spd) total 11.05 w primary and secondary channels enabled. 100% toggle on all channel lanes drams idle. 0 bw. cke high, command and address lines stable. dram clock active.
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 13 reference clock input specifications* 1 parameter symbol min. max. units notes reference clock frequency@ 4.0 gb/s (nominal 166.67mhz) frefclk-4.0 158.33 166.75 mhz 2 , 3, 4 single-ended maximum voltage vmax ? 1.15 v 5, 7 single-ended minimum voltage vmin ? 0.3 ? v 5, 8 differential voltage high vrefclk-diff-ih 150 ? mv 6 differential voltage low vrefclk-diff-il ? ? 150 mv 6 absolute crossing point vcross 250 550 mv 5, 9, 10 vcross variation vcross-delta ? 140 mv 5, 9, 11 ac common mode vsck-cm-acp-p ? 225 mv 12 rising and falling edge rates errefclk-diff-rise, errefclk-diff-fall 0.6 4.0 v/ns 6, 13 % mismatch between rise and fall edge rates errefclk-match ? 20 % 6, 14 duty cycle of reference clock trefclk-dutycycle 40 60 % 6 ringback voltage threshold vrb-diff ? 100 100 mv 6, 15 allowed time before ringback tstable 500 ? ps 6, 15 clock leakage current ii_ck ? 10 10 a 16, 17 clock input capacitance ci_ck 0.5 2.0 pf 17 clock input capacitance delta ci_ck ( ? ) ? 0.25 0.25 pf difference between refclk and refclk# input capacitance transport delay td ? 5 ns 18, 19 nsample 10 12 ? periods 20 reference clock jitter (rms), filtered tref-jitter-rms ? 3.0 ps 21, 22 reference clock jitter (peak-to-peak) due to spectrum clocking effects tref-sscp-p ? 30 ps reference clock jitter difference between adjacent amb tref-jitter- delta ? 0.75 ps 23 notes: 1. for details, refer to the jedec specificati on ?fb-dimm high speed differential ptp link at 1.5v?. 2. the nominal reference clock frequency is determined by the data frequency of the link divided by 2 times the fixed pll multiplication factor fo r the fb-dimm channel (6:1). fdata = 2000mhz for a 4.0gbps fb- dimm channel and so on. 3. measured with ssc disabled. enabling ssc will reduce the reference clock frequency. 4. not all fb-dimm agents will support all frequencie s; compliance to the frequency specifications is only required for those data rates that are supported by the device under test. 5. measurement taken from single-ended waveform. 6. measurement taken from differential waveform. 7. defined as the maximum instantaneous voltage including overshoot. 8. defined as the minimum instan taneous voltage including undershoot. 9. measured at the crossing poin t where the instantaneous voltage va lue of the rising edge of refclk+ equals the falling edge of refclk-. 10. refers to the total variation from the lowest cr ossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. 11. defined as the total variation of all crossing volt ages of rising refclk+ and falling refclk-. this is the maximum allowed variance in for any particular system. 12. the majority of the reference clock ac common mode occurs at high frequency (i.e., the reference clock frequency).
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 14 13. measured from ? 150mv to + 150mv on the differential waveform. the signal must be monotonic through the measurement region for rise and fall time. t he 300mv measurement windo w is centered on the differential 0v crossing. 14. edge rate matching applies to rising edge rate for refclk+ and falling edge rate for refclk-. it is measured using a 75mv window centered on th e median cross point where refclk+ rising meets refclk- falling. the median crosspoint is used to ca lculate the voltage thresholds the oscilloscope uses for the edge rate calculations. the rising edge rate of refclk+ should be compared to the falling edge rate of refclk-. the maximum allowed differ ence should not exceed 20% of the slowest edge 15. tstable is the time the differential clock must ma intain a minimum 150mv differential voltage after rising /falling edges before it is allowed to droo p back into the 100mv differential range. 16.measured with a single-ended input voltage of 1v. 17. applies to refclk and refclk#. 18. this parameter is not a direct clock output param eter but it indirectly det ermines the clock output parameter tref-jitter. 19. the net transport delay is the difference in time of flight between associated data and clock paths. the data path is defined from the reference clock source, through the tx, to data arrival at the data sampling point in the rx. the clock path is defined from the reference clock source to clock arrival at the same sampling point. the path delays are caused by copper trace routes, on-chip routing, on-chip buffering, etc. they include the time-of-flight of interpolat ors or other clock adjustment mechanisms. they do not include the phase delays caused by finite pll loop bandwidth because these delays are modeled by the pll transfer functions. 20. direct measurement of phase jitter records over nsam ple periods may be impractical. it is expected that the jitter will be measured over a smaller, yet statisti cally significant, sample si ze and the total jitter at nsample samples extrapolated from an estimate of the sigma of the random jitter components. 21. measured with ssc enabled on reference clock generator. 22. as ?measured? after the phase jitter filter. this number is separate from the rece iver jitter budget that is defined by the trx-to tal-min parameters. 23. this maximum value is below the noise floor of some test equipment.
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 15 differential transmitter output specifications* 1 parameter symbol min. max. unit comments differential peak-to-peak output voltage for large voltage swing vtx-diffp-p_l 900 1300 mv vtx-diffp-p = 2 | vtx-d+ ? vtx-d- | measured as note 2 differential peak-to-peak output voltage for regular voltage swing vtx-diffp-p_r 800 ? mv vtx-diffp-p = 2 | vtx-d+ ? vtx-d- | measured as note 2 differential peak-to-peak output voltage for small voltage swing vtx-diffp-p_s 520 ? mv vtx-diffp-p = 2 | vtx-d+ ? vtx-d- | measured as note 2 dc common code output voltage for large voltage swing vtx-cm_l ? 375 mv defined as: vtx-cm = dc (avg) of |vtx-d+ + vtx-d-|/2 measured as note 2 dc common code output voltage for small voltage swing vtx-cm_s 135 280 mv defined as: vtx-cm = dc (avg) of |vtx-d+ + vtx-d-|/2 measured as note 2. see also note 3 de-emphasized differential output voltage ratio for -3.5db de-emphasis vtx-de-3.5-ratio ? 3.0 ? 4.0 db 2, 4, 5 de-emphasized differential output voltage ratio for -6db de-emphasis vtx-de-6.0-ratio ? 5.0 ? 7.0 db 2, 4, 5 ac peak-to-peak common mode output voltage for large swing vtx-cm-acp-p l ? 90 mv vtx-cm-ac = max |vtx-d+ + vtx-d-|/2 ? min |vtx-d+ + vtx-d-|/2 measured as note 2. see also note 6 ac peak-to-peak common mode output voltage for regular swing vtx-cm-acp-p r ? 80 mv vtx-cm-ac = max |vtx-d+ + vtx-d-|/2 ? min |vtx-d+ + vtx-d-|/2 measured as note 2. see also note 6 ac peak-to-peak common mode output voltage for small swing vtx-cm-acp-p s ? 70 mv vtx-cm-ac = max |vtx-d+ + vtx-d-|/2 ? min |vtx-d+ + vtx-d-|/2 measured as note 2. see also note 6 maximum single-ended voltage in ei condition, dc + ac vtx-idle-se ? 50 mv 7, 8 maximum single-ended voltage in ei condition, dc only vtx-idle-se-dc ? 20 mv 7, 8, 9 maximum peak-to-peak differential voltage in ei condition vtx-idle-diffp-p ? 40 mv 8 single-ended voltage (w.r.t.vss) on d+/d- vtx-se ? 75 750 mv 2, 10 minimum tx eye width ttx-eye-min 0.7 ? ui 2, 11, 12 maximum tx deterministic jitter ttx-dj-dd ? 0.2 ui 2, 11, 12, 13 instantaneous pulse width ttx-pulse 0.85 ? ui 14 differential tx output rise/fall time ttx-rise, ttx-fall 30 90 ps given by 20%-80% voltage levels. measured as note 2 mismatch between rise and fall times ttx-rf-mismatch ? 20 ps differential return loss rltx-diff 8 ? db measured over 0.1ghz to 2.4ghz. see also note 15 common mode return loss rltx-cm 6 ? db measured over 0.1ghz to 2.4ghz. see also note 15
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 16 parameter symbol min. max. unit comments transmitter termination resistance rtx 41 55 ? 16 d+/d- tx resistance difference rtx-match-dc ? 4 % rtx-match-dc = 2 |rtx-d+ ? rtx-d-| / (rtx-d+ + rtx-d-) bounds are applied separately to high and low output voltage states lane-to-lane skew at tx ltx-skew 1 ? 100 + 3ui ps 17, 19 lane-to-lane skew at tx ltx-skew 2 ? 100 + 2ui ps 18, 19 maximum tx drift (resync mode) ttx-drift-resync ? 240 ps 20 maximum tx drift (resample mode only) ttx-drift- resample ? 120 ps 20 bit error ratio ber ? 10 -12 21 notes: 1. for details, refer to the jedec specificati on ?fb-dimm high speed differential ptp link at 1.5v?. 2. specified at the package pins into a ti ming and voltage compliance test load. common-mode measurements to be performed using a 101010 pattern. 3. the transmitter designer should not artificially elevate the common mode in order to meet this specification. 4. this is the ra tio of the vtx-diffp-p of the second and following bits after a transition divided by the vtx-diffp-p of the first bit after a transition. 5. de-emphasis shall be disabl ed in the calibration state. 6. includes all sources of ac common mode noise. 7. single-ended voltages below that value that are simultaneously detecte d on d+ and d- are interpreted as the electrical idle condition. 8. specified at the package pins into a voltage compli ance test load. transmitters must meet both single- ended and differential output ei specifications. 9. this specification, considered with vrx-idle-se-dc, implies a maximum 15mv single-ended dc offset between tx and rx pins during the electrical idle cond ition. this in turn allows a ground offset between adjacent fb-dimm agents of 26mv when worst case te rmination resistance matching is considered. 10. the maximum value is specified to be at leas t (vtx-diffp-p l / 4) + vtx-cm l + (vtx-cm-acp-p / 2) 11. this number does not include the e ffects of ssc or refe rence clock jitter. 12. these timing specifications apply to resync mode only. 13. defined as the dual-dirac deterministic jitter. 14. pulse width measured at 0 v differential. 15. one of the components t hat contribute to the deterioration of t he return loss is the esd structure which needs to be carefully designed. 16. the termination small signal resistance; tolera nce across voltages from 100mv to 400mv shall not exceed 5 ?. with regard to the average of the values measured at 100mv and at 400mv for that pin. 17. lane to lane skew at the transmitter pins for an end component. 18. lane to lane skew at the transmitter pins for an intermediate component (assuming zero lane to lane skew at the receiver pins of the incoming port). 19. this is a static skew. an fb-dimm component is not allowed to change its lane to lane phase relationship after initialization. 20. measured from the reference clock edge to the cent er of the output eye. this specification must be met across specified voltage and temperature ranges fo r a single component. drift rate of change is significantly below the tracking capability of the receiver. 21. ber per differential lane.
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 17 differential receiver input specifications* 1 parameter symbol min. max. unit comments differential peak-to-peak input voltage vrx-diffp-p 170 1300 mv vrx-diffp-p = 2 |vrx-d+ -vrx-d-| measured as note 2 maximum single-ended voltage for ei condition (ac + dc) vrx-idle-se ? 65 mv 3, 4, 5, 6 maximum single-ended voltage for ei condition (dc only) vrx-idle-se-dc ? 35 mv 3 , 4 , 5 , 6, 7 maximum peak-to-peak differential voltage for ei condition vrx-idle-diffp-p ? 65 mv 4 , 5 , 6 single-ended voltage (w.r.t. vss) on d+/d- vrx-se ? 300 900 mv 5 single-pulse peak differential input voltage vrx-diff-pulse 85 ? mv 5, 8 amplitude ratio between adjacent symbols, 1100mv < vrx-diffp-p <= 1300mv vrx-diff-adj ratio- hi ? 3.0 5, 9 amplitude ratio between adjacent symbols, vrx-diffp-p <= 1100mv vrx-diff-adj ratio ? 4.0 5, 9 maximum rx inherent timing error trx-tj-max ? 0.4 ui 5, 10, 11 maximum rx inherent deterministic timing error trx-dj-dd ? 0.3 ui 5, 10, 11, 12 single-pulse width at zero-voltage crossing trx-pw-zc 0.55 ? ui 5, 8 single-pulse width at minimum- level crossing trx-pw-ml 0.2 ? ui 5, 8 differential rx input rise/fall time trx-rise, trx-fall 50 ? ps given by 20%-80% voltage levels. common mode of the input voltage vrx-cm 120 400 mv defined as: vrx-cm = dc (avg) of |vrx-d+ + vrx-d-|/2 measured as note 2. see also note 13 ac peak-to-peak common mode of input voltage vrx-cm-acp-p ? 270 mv vrx-cm-ac = max |vrx-d+ + vrx-d-|/2 ? min |vrx-d+ + vrx-d-|/2 measured as note 2 ratio of vrx-cm-acp-p to minimum vrx-diffp-p vrx-cm-eh-ratio ? 45 % 14 differential return loss rlrx-diff 9 ? db measured over 0.1ghz to 2.4ghz. see also note 15 common mode return loss rlrx-cm 6 ? db measured over 0.1ghz to 2.4ghz. see also note 15 rx termination resistance rrx 41 55 ? 16 d+/d- rx resistance difference rrx-match-dc ? 4 % rrx-match-dc = 2 |rrx-d+ ? rrx-d-| / (rrx-d+ + rrx-d-) lane-to-lane pcb skew at rx lrx-pcb-skew ? 6 ui lane-to-lane pcb skew at the receiver that must be tolerated. see also note 17 minimum rx drift tolerance trx-drift 400 ? ps 18 minimum data tracking 3db bandwidth ftrk 0.2 ? mhz 19 electrical idle entry detect time tei-entry - detect ? 60 ns 20 electrical idle exit detect time tei-exit -detect ? 30 ns bit error ratio ber ? 10 -12 21
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 18 notes: 1. for details, refer to the jedec specificati on ?fb-dimm high speed differential ptp link at 1.5v?. 2. specified at the package pins into a timing and voltage compliant test se tup. note that signal levels at the pad will be lower than at the pin. 3. single-ended voltages below that value that are simultaneously detecte d on d+ and d- are interpreted as the electrical idle condition. worst-case margins ar e determined by comparing ei levels with common mode levels during normal operation for the case with transmitter using small voltage swing. 4. multiple lanes need to detect the ei condition before the device can act upon the ei detection. 5. specified at the package pins into a timing and voltage compliance test setup. 6. receiver designers may implement either single-ende d or differential ei detection. receivers must meet the specification that corresponds to the implemented detection circuit. 7. this specification, considered with vtx-idle- se-dc, implies a maximum 15mv single-ended dc offset between tx and rx pins during the electrical idle condit ion. this in turn allows a ground offset between adjacent fb-dimm agents of 26mv when worst case te rmination resistance matching is considered. 8. the single-pulse mask provides sufficient symbol en ergy for reliable rx reception. each symbol must comply with both the single-pulse mask and the cumulative eye mask. 9. the relative amplitude ratio limit between adjacent symbols prevents excessive inter-symbol interference in the rx. each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols. 10. this number does not include the e ffects of ssc or refe rence clock jitter. 11. this number includes setup a nd hold of the rx sampling flop. 12. defined as the dual-dirac deterministic timing error. 13. allows for 15mv dc offset between transmit and receive devices. 14. the received differential signal must satisfy both this ratio as well as the absolute maximum ac peak-to- peak common mode specification. for example, if vrx-diffp-p is 200mv, the maximum ac peak-to- peak common mode is the lesser of (200mv 0.45 = 90mv) and vrx-cm-acp-p. 15. one of the components t hat contribute to the deterioration of t he return loss is the esd structure which needs to be carefully designed. 16. the termination small signal resistance; tolera nce across voltages from 100mv to 400mv shall not exceed 5 ?. with regard to the average of the values measured at 100mv and at 400mv for that pin. 17. this number represents the lane-to-lane skew bet ween tx and rx pins and does not include the transmitter output skew from the component driving the signal to the receiver. this is one component of the end-to-end channel skew in the amb specification. 18. measured from the reference clock edge to the cent er of the input eye. this specification must be met across specified voltage and temperature ranges fo r a single component. drift rate of change is significantly below the tracking capability of the receiver. 19. this bandwidth number assumes the specified minimu m data transition density. maximum jitter at 0.2mhz is 0.05ui. 20. the specified time includes the time r equired to forward the ei entry condition. 21. ber per differential lane.
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 19 serial pd matrix for fb-dimm byte no. function described byte value hex value 0 number of serial pd bytes written / spd device size / crc coverage 116 92h 1 spd revision revision 1.1 11h 2 key byte / dram device type ddr2 sdram fb-dimm 09h 3 voltage levels of this assembly vdd = 1.8v, vcc = 1.5v 12h 4 sdram addressing 14-row, 11-column, 8-bank 49h 5 module physical attributes 8.2mm 24h 6 module type / thickness fb-dimm 07h 7 module organization 4 ranks / 4bits 20h 8 fine timebase (ftb) di vidend / divisor 00h 9 medium timebase dividend 1 01h 10 medium timebase divisor 4 04h 11 sdram minimum cycle time (tck (min.)) 3.00ns 0ch 12 sdram maximum cycle time (tck (max.)) 8ns 20h 13 sdram /cas latencies supported cl = 3, 4, 5 33h 14 sdram minimum /cas latencies time (tcas) 15ns 3ch 15 sdram write recovery times supported wr = 2 to 5 42h 16 sdram write recovery time (twr) 15ns 3ch 17 sdram write latencies supported wl = 2 to 8 72h 18 sdram additive latencies supported al = 0 to 4 50h 19 sdram minimum /ras to /cas delay (trcd) 15ns 3ch 20 sdram minimum row active to ro w active delay (trrd) 7.5ns 1eh 21 sdram minimum row prechar ge time (trp) 15ns 3ch 22 sdram upper nibbles for tras and trc 00h 23 sdram minimum active to pr echarge time (tras) 45ns b4h 24 sdram minimum auto-refresh to active /auto-refresh time (trc) 60ns f0h 25 sdram minimum refresh recovery time delay (trfc), lsb 127.5ns feh 26 sdram minimum refresh recovery time delay (trfc), msb 127.5ns 01h 27 sdram internal write to read command delay (twtr) 7.5ns 1eh 28 sdram internal read to precharge command delay (trtp) 7.5ns 1eh 29 sdram burst lengths supported bl = 4, 8 03h 30 sdram terminations supported odt = 50, 75, 150 ? 07h 31 sdram drivers supported supported 01h 32 sdram average refresh interval (t refi) / double refresh mode bit / high temperature self-refresh rate support indication 7.8 s double/ht refresh c2h 33 tcasemax (tc (max.)) delta / dt4r4w delta 95 c/ 0.40 c 51h 34 psi t-a sdram at still air * 3 35 sdram dt0 * 3 36 sdram dt2q * 3 37 sdram dt2p * 3 38 sdram dt3n * 3 39 sdram dt4r / mode bit * 3 40 sdram dt5b * 3 41 sdram dt7 * 3
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 20 byte no. function described byte value hex value 42 to 74 reserved 00h 75 amb qr control setting qr = enable 01h 76 reserved 00h 77 reserved 00h 78 fbd odt definition for ranks 2 and 3 disable 00h 79 fbd odt definition for ranks 0 and 1 150/150 ? 22h 80 reserved 00h 81 to 93 amb personality bytes 94 to 97 reserved 00h 98 amb case temperature maximum (tcase (max.)) 99 category byte ddp/fdhs 12h 100 reserved 00h 101 to 116 amb personality bytes 117 module id: manufacturer?s jedec id code elpida memory 02h 118 module id: manufacturer?s je dec id code elpida memory feh 119 module id: manufacturing location 120 module id: manufacturing date year code (bcd) 121 module id: manufacturing date date code (bcd) 122 to 125 module id: module serial number 126 to 127 cyclical redundancy code 128 to 145 module part number ebe82ff4a1rq 146 module revision code initial 30h 147 module revision code (space) 20h 148 sdram manufacturer?s jedec id code elpida memory 02h 149 sdram manufacturer?s jedec id code elpida memory feh 150 informal amb content revision tag (msb) 151 informal amb content revision tag (lsb) 152 to 175 manufacturer's specific data 00h 176 to 255 open for customer use 00h remark idd: dram current, icc: amb current notes: 1. based on ddr2 sdra m component specification. 2. refer to jesd51-3 ?low effective thermal cond uctivity test board for leaded surface mount packages? under jesd51-2 standard. 3. dt parameter is derived as following: dtx = iddx vdd psi t-a, where iddx definition is based on jedec ddr2 sdram component specification and at vd d=1.9v, it is the datasheet (worst case) value, and psi t-a is the programmed value of psi t-a (value in spd byte 33).
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 21 physical outline detail a 0.20 0.15 2.50 0.20 1.00 0.80 0.05 3.00 5.00 detail b 3.80 1.50 0.10 2.50 full r (datum -a-) eca-ts2-0244-01 full r 1 120 unit: mm front side back side tie bar keep out zone 0.40 min. 17.30 30.35 3.90 67.00 51.00 a 9.50 74.675 1.25 5.175 2.50 r0.75 (datum -a-) full dimm heat spreader b 120 240 121 amb 133.35 d1 d37 4.00 min. 1.27 0.10 8.20 max. 5.20 max. 3.00 max. d3 d39 d4 d40 d6 d42 d0 d36 d2 d38 d5 d41 d7 d43 d10 d46 d12 d48 d13 d49 d15 d51 d9 d45 d11 d47 d14 d50 d16 d52 d18 d54 d20 d56 d23 d59 d25 d61 d19 d55 d21 d57 d22 d58 d24 d60 d27 d63 d29 d65 d32 d68 d34 d70 d28 d64 d30 d66 d31 d67 d33 d69 d8 d44 d17 d53 d26 d62 d35 d71
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 22 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. in particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0202 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
ebe82ff4a1rq preliminary data sheet e1242e20 (ver. 2.0) 23 m01e0706 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] be aware that this product is for use in typical electronic equipment for general-purpose applications. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] usage in environments with special characteristics as listed below was not considered in the design. accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. example: 1) usage in liquids, including water, oils, chemicals and organic solvents. 2) usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) usage involving exposure to significant amounts of corrosive gas, including sea air, cl 2 , h 2 s, nh 3 , so 2 , and no x . 4) usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) usage in places where dew forms. 6) usage in environments with mechanical vibration, impact, or stress. 7) usage near heating elements, igniters, or flammable items. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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